1. Technical Field
The present invention relates generally to Integrated Circuit (IC) memory devices and more specifically to entry of an integrated circuit memory device into a test mode.
2. Discussion of the Prior Art
Integrated circuit memory devices are routinely subjected to myriad types of test modes. These test modes may be used to subject the integrated circuit device to functional testing, to burn-in testing, and to stress testing, to name just a few examples of testing.
A major concern with integrated circuit devices capable of entering a test mode to be tested is accidental entry into the test mode when the device is not to be tested. Such false entry of an integrated circuit memory device into a test mode is typically caused by a voltage spiking condition of a voltage supplied to the integrated circuit memory device. False entry is exacerbated when the integrated circuit is placed in a noisy environment.
There is thus a need in the art to prevent false entry of an integrated circuit device into a test mode when the device is not to be tested. Any means for preventing false entry of the device into the test mode should protect the device while in a noisy environment in which the device may be subjected to a voltage spiking condition of a supply voltage.